应用介绍

此项目是VHDL中的密码协处理器设计。

在此VHDL项目中，在VHDL中设计和实现了用于密码应用程序的完整协处理器。如先前的Verilog / VHDL项目中所述，协处理器提供了针对安全性的标准指令和专用功能单元。 协处理器是在VHDL中设计和实现的，而ALU单元中的N位加法器是在Verilog中实现的。

协处理器的框图如下：

首先，让我们实现协处理器的组合逻辑单元。 以下是组合逻辑单元的框图：

协处理器的指令集架构如下：

0. ADD: ABUS + BBUS -> RESULT
1. SUB: ABUS - BBUS -> RESULT
2. AND: ABUS & BBUS -> RESULT
3. OR: ABUS | BBUS -> RESULT
4. XOR: ABUS ^ BBUS -> RESULT
5. NOT: ~ABUS -> RESULT
6. MOV: ABUS -> RESULT

7. NOP: No Operation
8. ROR8: RESULT<= SHIFTINPUT(7 downto 0)&SHIFTINPUT(15 downto 8) ;
9. ROR4: RESULT<= SHIFTINPUT(3 downto 0)&SHIFTINPUT(15 downto 4) ;
10. SLL8: RESULT<= SHIFTINPUT(7 downto 0) & "00000000";

11. LUT: RESULT <= OUTPUT of LOOKUP TABLE Implementation

附件中包括：协处理器组合逻辑单元的VHDL代码、寄存器文件的VHDL代码、完整协处理器的VHDL代码、加密协处理器的VHDL Testbench代码、密码协处理器的仿真波形。

本人在下方展示了协处理器组合逻辑单元的VHDL代码；如想了解更多请下载附件。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: Cryptographic coprocessor Design in VHDL
-- VHDL code for Combinational Logic unit of the coprocessor
entity structural_VHDL is
port ( A_BUS: in std_logic_vector(15 downto 0);
   B_BUS: in std_logic_vector(15 downto 0);
   CTRL: in std_logic_vector(3 downto 0);
   RESULT: out std_logic_vector(15 downto 0)
  );
end structural_VHDL;
architecture Behavioral of structural_VHDL is
component non_linear_lookup is
port (  LUTIN: in std_logic_vector(7 downto 0);
   LUTOUT: out std_logic_vector(7 downto 0)
 );
end component non_linear_lookup;
component shifter is
  generic ( N: integer:=16
  );
    Port ( SHIFTINPUT : in  STD_LOGIC_VECTOR(N-1 downto 0);
   SHIFT_Ctrl : in  STD_LOGIC_VECTOR(3 downto 0); 
   SHIFTOUT: out  STD_LOGIC_VECTOR(N-1 downto 0)
  );
end component shifter;
component ALU is
 port (
   ABUS: in std_logic_vector(15 downto 0);
   BBUS: in std_logic_vector(15 downto 0);
   ALUctrl: in std_logic_vector(3 downto 0);
   ALUOUT: out std_logic_vector(15 downto 0)
   );
end component ALU;
signal tmp_out1,tmp_out2,tmp_out3: std_logic_vector(15 downto 0);
signal lut_out: std_logic_vector(7 downto 0);
begin
-------------
-- ALU Unit--
-------------
ALU_unit: ALU port map( ABUS => A_BUS, BBUS => B_BUS,ALUctrl => CTRL,ALUOUT => tmp_out1); 
-----------------
-- Shifter Unit--
-----------------
shifter_unit: shifter generic map ( N => 16) -- shifter
 port map( SHIFTINPUT => B_BUS, SHIFT_Ctrl => CTRL,SHIFTOUT => tmp_out2 ); 
-------------------------------------
-- Non-linear Lookup Operation Unit--
-------------------------------------
non_linear_lookup_unit: non_linear_lookup
 port map( LUTIN => A_BUS(7 downto 0), LUTOUT => lut_out);
 tmp_out3 <= A_BUS(15 downto 8) & lut_out;
-----------------------
-- Control Logic Unit--
-----------------------
control_logic: process(CTRL,tmp_out1,tmp_out3,tmp_out2) begin
  case(CTRL(3 downto 3)) is
  when "0" => 
    RESULT <= tmp_out1;
  when others => 
    case(CTRL(1 downto 0)) is
    when "11" =>
     RESULT <= tmp_out3;
    when others =>
     RESULT <= tmp_out2;
    end case;
  end case;
 end process control_logic;
 
end Behavioral;